Agilent Technologies 93000 SOC Series Training Manual page 618

Mixed-signal training
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TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
Appendix D
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
functional block diagram
Resistor
Reference
Divider
REFB
270 Ω
NOM
REFT
REFBS
80 Ω
NOM
AGND
AGND
V DDA
320 Ω
NOM
REFTS
ANALOG IN
Clock
CLK
Generator
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
V DDA
ANALOG IN
AGND
2
Lower Sampling
Comparators
(4-Bit)
Lower Sampling
Comparators
(4-Bit)
Upper Sampling
Comparators
(4-Bit)
EQUIVALENT OF EACH DIGITAL INPUT
V DDD
OE, CLK
DGND
618
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OE
Lower Encoder
(4-Bit)
Lower Data
Latch
Lower Encoder
(4-Bit)
Upper Data
Latch
Upper Encoder
(4-Bit)
EQUIVALENT OF EACH DIGITAL OUTPUT
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
V DDD
D1 – D8
DGND

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