Ppg1/3/5 Operation Mode Control Register (Ppgc1) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 17 8/16-BIT PPG TIMER

17.2.2 PPG1/3/5 Operation Mode Control Register (PPGC1)

This section describes the configuration and functions of the PPG1/3/5 operation
mode control register (PPGC1).
I PPG1/3/5 operation mode control register (PPGC1)
The PPG1/3/5 operation mode control register (PPGC1) is used to select the channel 1/3/5
operation mode, control pin output, and select the count clock. It is also used for trigger control.
The bit configuration of the PPG1/3/5 operation mode control register (PPGC1) is shown below.
15
00003B
H
00003D
PEN1
H
00003F
H
(R/W)
(0)
The functions of the bits in the PPG1/3/5 operation mode control register (PPGC1) are
described below.
[Bit 15] PEN1: ppg Enable (operation enable)
This bit is used to start PPG operation and select the operation mode.
PEN0
0
1
• When this bit is set to "1", PPG count starts.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[Bit 14] PE10: ppg output Enable 10 (PPG1/3/5 output pin enable)
This bit is used to allow or prohibit pulse output to the pulse output external pin PPG1/3/5.
PE00
0
1
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
336
14 13 12 11
- PE10 PIE1 PUF1 MD1 MD0
(-) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (0) (0) (0)
Operation state
Operation stop ("L" level output is retained)
PPG operation enabled
Operation state
General-purpose port (pulse output prohibited)
PPG1/3/5 pulse output (pulse output allowed)
10 9 8 PPGC1/3/5
Operation mode control register
Reserved
(-) Reading/writing
(0) (0) (1) Initial value