Fujitsu F2MC-16LX Hardware Manual page 530

APPENDIX
Table A-3 Relationship between interrupt sources and interrupt vector/interrupt control registers
Interrupt source
Output compare (ch5) match
UART transmit completed
16-bit free-run timer/16-bit reload
timer
UART receive completed
SI01
SI02
2
I C interface
A/D
FLASH write/delete, timebase timer/
watch timer
Delay interrupt generate module
: Interrupt clear signal clears the interrupt request flag. A stop request is issued.
: Interrupt clear signal clears the interrupt request flag.
x: Interrupt clear signal will not clear the interrupt request flag.
*1: Make sure that FLASH write/delete operations are not used during operation of the timebase timer and
watch timer.
Note 1: If the same interrupt number is assigned to two interrupt sources, the resource is cleared only if both
interrupt request flags are cleared by DMAC interrupt clear signals. Therefore, if either of two interrupt
functions uses the DMAC function, the other interrupt function cannot be used. Set the relevant resource's
interrupt request enable bit to "0" and use software polling processing to handle this situation.
514
2
EI OS
clear
x
x
*1
x
µ µ µ µ DMA
Interrupt vector
channel
number
Number
x #33
11 #34
12 #35
7 #36 FFFF6C
13 #37
14 #38
x #39
15 #40 FFFF5C
x #41
x #42
Interrupt control
register
Address Number Address
FFFF78
H
ICR11 0000BB
FFFF74
H
FFFF70
H
ICR12 0000BC
H
FFFF68
H
ICR13 0000BD
FFFF64
H
FFFF60
H
ICR14 0000BE
H
FFFF58
H
ICR15 0000BF
FFFF54
H
H
H
H
H
H