Flow Of Hardware Interrupt Operation - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.4.2

Flow of Hardware Interrupt Operation

If an interrupt request is generated by a peripheral function, the interrupt controller
transfers its interrupt level to the CPU. If the CPU accepts the interrupt request, the
instruction currently being executed is temporarily suspended to execute the interrupt
processing routine or to start µ µ µ µ DMA/Extended intelligent I/O service (EI
software interrupt is generated by the INT instruction, the interrupt processing routine
is executed regardless of the CPU state. Moreover, if a software interrupt is generated
by the INT instruction, the hardware interrupt is prohibited.
I Hardware interrupt operation flow
Figure 3.4-3 "Flow of hardware interrupt operation" shows the hardware interrupt operation flow.
START
I&IF&IE=1
String-type
instruction being
executed*1
Reading and decoding
of next instruction
INT instruction?
RETI instruction?
Execution of normal instruction
(Including interrupt processing)
Completed
NO
reiteration of string-type
instruction*1
Moving of pointer to next
instruction if PC updated
*1 : When a string-type instruction is being executed, the
interrupt condition is checked in each step.
I : Interrupt permission flag of condition code register
(CCR)
IF : Interrupt request flag of peripheral function
IE : Interrupt permission flag of peripheral function
ILM : Interrupt level mask register (in PS)
60
Figure 3.4-3 Flow of hardware interrupt operation
Main program
YES
AND
ILM>IL
NO
YES
Storing dedicated registers
NO
in the system stack
I
Hardware interrupt
prohibited
YES
NO
Return of dedicated registers
from system stack and then
its return to routine that
existed before calling of
interrupt routine
YES
ENx=1?
NO
Software
interrupt and
exception
processing
YES
Hardware
interrupt
Storing dedicated registers
in the system stack
0
ILM IL
(If an interrupt request is
accepted, its interrupt
level is transferred to ILM.)
Execution of
S 1
interrupt return
(Enabling system stack)
PCB, PC Interrupt vector
(Branching to interrupt
processing routine)
ENx : Request flag executing DMA of DMA enable register
(DER)
IL : Interrupt level setting bit in interrupt control register
(ICR)
S : Stack flag in condition code register (CCR)
PCB : Program bank register
PC : Program counter
2
OS). If a
Interrupt start and return processing
µDMA/EI 2
OS
YES
µDMA/EI
2
OS processing
Has the
specified number of
times been completed?
Or did a peripheral function
issue a complete
request?
NO