Dtp/External Interrupt Unit Registers - Fujitsu F2MC-16LX Hardware Manual

18.2 DTP/External Interrupt Unit Registers

This section describes the configuration and functions of the registers used in the
DTP/external interrupt unit.
I List of registers of DTP/external interrupt unit
Figure 18.2-1 "List of DTP/external interrupt unit registers" shows a list of the registers of the
DTP/external interrupt unit.
Bit
Address: 00000C
EN7
H
Bit
Address: 00000D
ER7
H
Bit
Address: 00000E
H
Bit
Address: 00000F
H
I Interrupt/DTP enable register (ENIR: Enable interrupt request register)
The bit configuration of the interrupt/DTP enable register (ENIR) is shown below.
ENIR
address: 00000C
The Interrupt/DTP enable register (ENIR) uses a device pin as external interrupt/DTP request
input, and determines whether to start a function for generating a request for the interrupt
controller. The pins corresponding to register bits set to "1" are used as external interrupt/DTP
request input for generating a request for the interrupt controller. The pins corresponding to bits
set to "0" retain external interrupt/DTP request input sources, but are not used for generating
requests for the interrupt controller.
Figure 18.2-1 List of DTP/external interrupt unit registers
7 6 5 4
EN6 EN5 EN4 EN3
15 14 13 12
ER6 ER5 ER4 ER3
7 6 5 4
LB3 LA3 LB2 LA2
15 14 13 12
LB7 LA7 LB6 LA6
7 6 5
EN7 EN6 EN5 EN4 EN3
H
R/W R/W R/W R/W R/W
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT
3 2 1 0
EN2 EN1 EN0
11 10 9 8
ER2 ER1 ER0
3 2 1 0
LB1 LA1 LB0 LA0
11 10 9 8
LB5 LA5 LB4 LA4
4 3 2 1
EN2 EN1 EN0
R/W R/W R/W
Interrupt/DTP enable register
(ENIR)
Interrupt/DTP source register
(EIRR)
Request level setting register
(ELVR)
Request level setting register
(ELVR)
0 Initial value
00000000
B
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