Fujitsu F2MC-16LX Hardware Manual page 282

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
Figure 13.3-2 Outline of phase difference count mode (at frequency multiplied by 4) operation
AIN pin
BIN pin
+1 +1 +1
Count value 0
1 2
In counting the encoder output, the input condition must be arranged by defining the relationship
between the phases and pins shown below. Thus, high-precision detection can enable the
rotation angle, rotation count, and rotation direction to be measured.
• Inputting phase A to the AIN pin
• Inputting phase B to the BIN pin
• Inputting phase Z to the ZIN pin
If this count mode is selected, the selection of detect edge via CCRH: CES1/0 and CCRL:
CGE1/0 is disabled.
266
+1 +1 +1 +1 +1 +1
3 4 5 6 7 8 9
+1 -1 +1 -1
10 9 10 9
-1 -1 -1 -1 -1 -1 -1 -1
8 7 6 5 4 3 2 1