Ppg1 Operation Mode Control Register (Ppgc1) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

14.3.2 PPG1 operation mode control register (PPGC1)

PPG1 operation mode control register
Address: ch0 000045H
PPGC0 is a seven-bit control register that selects the operation mode of the block, controls pin outputs,
selects count clock, and controls triggers.
[bit 15] PEN1 (PPG enable): Operation enable bit
This bit selects the PPG operation mode as described below.
PEN1
0
1
Setting this bit to 1 makes the PWM start counting.
This bit is initialized to '0' upon a reset. This bit is readable and writable.
[bit 13] PE10 (PPG output enable 1): PPG1 pin output enable bit
PE10
0
1
This bit controls the PPG1 pulse output external pin as described below.
This bit is initialized to '0' upon a reset. This bit is readable and writable.
[bit 12] PIE1 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG interrupt as described below.
PIE1
0
1
While '1' is set in this bit, an interrupt request is issued as soon as '1' is written to PUF1. No interrupt
request is issued while this bit is set to '0.'
This bit is initialized to '0' upon a reset. This bit is readable and writable.
Note: PIE1 is assigned the same interrupt vector number as that of UART 0 transmission
complete. When using EI
MB90580 Series
15
PEN1
(R/W)
Read/write
(0)
Initial value
Operation
Stop ('L' level output maintained)
PPG operation enabled
General-purpose port pin (pulse output disabled)
PPG1 = pulse output pin (pulse output enabled)
Operation
Interrupt disabled
Interrupt enabled
2
OS in UART 0 transmissioin complete, write '0' to PIE1.
14 13 12 11
PE10 PIE1 PUF1 MD1 MD0
(-) (R/W) (R/W) (R/W)
(X) (0) (0) (0)
[initial value]
Operation
[initial value]
14.3 Registers and Register Details
10 9 8
Reserved
(-)
(R/W) (R/W)
(1)
(0) (0)
[initial value]
Chapter 14: 8/16-Bit PPG
Bit No.
PPGC1
197