Fujitsu F2MC-16LX Hardware Manual page 49

I Interrupt level mask register (ILM)
The interrupt level mask register (ILM) consists of 3 bits indicating the level of the CPU interrupt
mask. Only an interrupt level higher than that represented with the 3 bits is accepted. The
highest level is indicated with 0, the lowest level is indicated with 7 (see Table 2.3-1 ). Thus, to
accept an interrupt, its level must be lower than the current ILM value.
accepted, its interrupt level value is set to ILM, and then any interrupts with the same or lower
level of the interrupt priority are not accepted.
instruction can transfer an 8-bit immediate value to the ILM register, but only the lower 3 bits are
actually used.
Figure 2.3-9 "Configuration of interrupt level mask register" shows the configuration of the
interrupt level mask register. Table 2.3-1 has explanations of the level indicated in the interrupt
level mask register (ILM).
Table 2.3-1 Level indicated by interrupt level mask register (ILM)
ILM2
0
0
0
0
1
1
1
1
Figure 2.3-9 Configuration of interrupt level mask register
Initial value
ILM1
0
0
1
1
0
0
1
1
ILM is initialized to zero by a reset.
ILM2 ILM1 ILM0
0 0 0
ILM0 Level value
0 0
1 1
0 2
1 3
0 4
1 5
0 6
1 7
CHAPTER 2 CPU
If an interrupt is
Permitted interrupt level
Interrupt prohibited
0 only
Level value less than 1
Level value less than 2
Level value less than 3
Level value less than 4
Level value less than 5
Level value less than 6
An
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