Fujitsu F2MC-16LX Hardware Manual page 96

CHAPTER 3 INTERRUPT
❍ Transfer performance
Minimum transfer speed
1.7 µs/10 MHz (machine clock)
1.07 µs/16 MHz (machine clock)
• Built-in I/O -> built-in RAM; or built-in RAM -> built-in I/O without address increment
• Even-numbered address -> even-numbered address or 8-bit access
Maximum transfer speed
2.8 µs/10 MHz (machine clock)
1.75 µs/16 MHz (machine clock)
Table 3.6-4 "Correction values (Z) for interrupt handling time" indicates the correction values for
interrupt handling time.
Table 3.6-4 Correction values (Z) for interrupt handling time
Address indicated by stack pointer
External 8 bit
External even-numbered address
External odd-numbered address
Internal even-numbered address
Internal odd-numbered address
❍ If a transfer is ended with an end request from a peripheral function (I/O)
If a µDMA data transfer ends partway (DEx = 1) because of an end request by a peripheral
function (I/O), the data transfer fails and a hardware interrupt starts. The µDMA processing time
in this case is calculated with the following formula. Z in the formula indicates a correction value
for interrupt processing time (see Table 3.6-3 "Correction values of data transfer for µDMA
execution time").
The µDMA processing time if a transfer ends partway is:
36 + 6 x Z machine cycle
where one machine cycle corresponds to one clock interval of the machine clock (φ).
80
Correction value (Z)
+4
+1
+4
0
+2