Fujitsu F2MC-16LX Hardware Manual page 214

CHAPTER 9 TIMEBASE TIMER
Table 9.5-1 Timebase timer clear operation and oscillation stabilization wait time.
Writing "0" to initializing bit
(TBR) for timebase timer
control register (TBTC)
Power-on reset
Watchdog reset
Release of the main stop
mode
Release of the PLL stop
mode
Release of the sub stop
mode
Switching from main clock
mode to PLL clock mode
(MCS: transition from 1 to 0)
Transition from sub-clock
mode to main clock mode
(SCS: transition from 0 to 1)
Release of timebase timer
mode
Release of sleep mode
: Cleared
x: Not cleared
I Clock supplying function
The timebase timer supplies a clock to the watchdog timer. Clearing of the timebase timer
counter affects the operation of the watchdog timer.
198
Counter
Operation
TOBF
Oscillation stabilization wait time
clear clear
Oscillation stabilization wait time of
main clock
x
Oscillation stabilization wait time of
main clock
Oscillation stabilization wait time of
x x
sub-clock
Oscillation stabilization wait time of
PLL clock
Oscillation stabilization wait time of
x x
main clock
x x Not provided
x x Not provided
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