Reload Registers (Ppll0 To Ppll5, Pplh0 To Pplh5) - Fujitsu F2MC-16LX Hardware Manual

17.2.4 Reload Registers (PPLL0 to PPLL5, PPLH0 to PPLH5)

This section describes the configuration and functions of the reload registers (PPLL0
to PPLL5, PPLH0 to PPLH5).
I Reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5)
The bit configuration of the reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5) is shown
below.
00002E
H
000030
H
000032
H
000034
H
000036
H
000038
H
00002F
H
000031
H
000033
H
000035
H
000037
H
000039
H
The reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5) are 8-bit registers which each store a
reload value for the down counter (PCNT). The registers have the following functions.
Register name
PRLL
PRLH
• Both registers can be read and written.
Note:
If PRLL and PRLH for channels 0/2/4 are set to different values in 8-bit prescaler/8-bit PPG
mode, the PPR waveform of channels 1/3/5 may differ from cycle to cycle. It is therefore
recommended that PRLL and PRLH for channels 0/2/4 be set to the same value.
7 6 5 4
D07 D06 D05 D04
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write
(X) (X) (X) (X)
15 14 13 12
D15 D14 D13 D12
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write
(X) (X) (X) (X)
Function
Stores the L-side reload value
Stores the H-side reload value
CHAPTER 17 8/16-BIT PPG TIMER
3 2 1 0
D03 D02 D01 D00
(X) (X) (X) (X)
11 10 9 8
D11 D10 D09 D08
(X) (X) (X) (X)
PPLL0 to -5
Reload register "L"
Initial value
PPLH0 to -5
Reload register "H"
Initial value
341