Fujitsu F2MC-16LX Hardware Manual page 14

21.3.2 Operation in Synchronous Mode (Operation Mode 2) ................................................................. 413
21.3.3 Two-Way Communication Function (Normal Mode) .................................................................... 415
21.3.4 Master/Slave Communication Function (Multiprocessor Mode) .................................................. 417
21.4 Precautions on Using the UART ....................................................................................................... 420
21.5 UART Program Example .................................................................................................................. 421
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CHAPTER 22 I C INTERFACE ........................................................................................ 423
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22.1 Overview of I C Interface .................................................................................................................. 424
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22.2 I C Interface Registers ...................................................................................................................... 426
22.2.1 Bus Status Register (IBSR) ......................................................................................................... 427
22.2.2 Bus Control Register (IBCR) ........................................................................................................ 429
22.2.3 Clock Control Register (ICCR) ..................................................................................................... 432
22.2.4 Address Register (IADR) ............................................................................................................. 434
22.2.5 Data Register (IDAR) ................................................................................................................... 435
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22.3 I C Interface Operation ..................................................................................................................... 436
CHAPTER 23 CHIP SELECTION FACILITY ................................................................... 439
23.1 Overview of Chip Selection Facility ................................................................................................... 440
23.2 Registers of Chip Selection Facility .................................................................................................. 441
23.2.1 Chip Select Area MASK Register (CMRx) ................................................................................... 442
23.2.2 Chip Selection Area Register (CARx) .......................................................................................... 443
23.2.3 Chip Selection Control Register (CSCR) ..................................................................................... 444
23.2.4 Chip Selector Active Level Register (CALR) ................................................................................ 445
23.3 Operation of the Chip Selection Facility ............................................................................................ 446
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION .......................................... 449
24.1 Overview of Address Match Detection Function ............................................................................... 450
24.2 Block Diagram of Address Match Detection Function ....................................................................... 451
24.3 Configuration of Address Match Detection Function ......................................................................... 452
24.3.1 Address Detection Control Register (PACSR) ............................................................................. 453
24.3.2 Detect Address Setting Registers (PADR0H and PADR1) ......................................................... 455
24.4 Explanation of Operation of Address Match Detection Function ...................................................... 457
24.4.1 Example of using Address Match Detection Function ................................................................. 458
24.5 Program Example of Address Match Detection Function ................................................................. 463
CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE ................................. 465
25.1 Overview of ROM Mirror Function Select Module ............................................................................. 466
25.2 ROM Mirror Function Select Register (ROMM) ................................................................................ 467
CHAPTER 26 2M BIT FLASH MEMORY ......................................................................... 469
26.1 Overview of 2M Bit Flash Memory .................................................................................................... 470
26.2 Sector Configuration of 2M Bit Flash Memory .................................................................................. 471
26.3 Control Status Register (FMCS) ....................................................................................................... 472
26.4 Method for Starting the Flash Memory's Automatic Algorithm .......................................................... 475
26.5 Verifying the Execution State of the Automatic Algorithm ................................................................. 476
26.5.1 Data Polling Flag (DQ7) ............................................................................................................... 478
26.5.2 Toggle Bit Flag (DQ6) .................................................................................................................. 480
26.5.3 Timing Limit Excess Flag (DQ5) .................................................................................................. 481
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