Fujitsu F2MC-16LX Hardware Manual page 591

chip/sector sector erase operation....................... 478
clearing counter ................................................... 270
clearing timer ....................................................... 292
clock control register (ICCR) ................................ 432
clock generator, block diagram of, ....................... 116
clock mode........................................................... 129
clock mode, change of ......................................... 121
clock selection register (CKSCR), configuration of
................................................................... 118
clock supply map ................................................. 115
clock supplying function ............................... 191, 198
clock, overview of................................................. 114
command sequence table.................................... 475
common register bank prefix (CMR) ...................... 39
communication prescaler control register (CDCR)
................................................................... 404
compare clear register (CPCLR).......................... 228
compare function ................................................. 268
compare register (OCCP0 to 5) ........................... 233
conditioncode register (CCR)................................. 31
configuration of extended intelligent I/O service
(El2OS) descriptor (ISD) .............................. 83
configuration of interrupt control register (ICR)...... 52
continuous prefix code ........................................... 40
control register (OCS0 to 5) ................................. 234
control status register (FMCS) ............................. 472
control status register (ICS01) ............................. 238
control status register 1 (ADCS1) ........................ 359
control status register 2 (ADCS2) ........................ 362
conversion data protection function ..................... 374
conversion data protection function operation (when
DMAC is used), operation flow of .............. 375
conversion data protection function, caution
when using................................................. 374
count clear/gate function...................................... 270
count clock ........................................................... 293
count clock selection............................................ 288
count clock, selection of....................................... 344
count direction flag............................................... 271
count direction reversal flag ................................. 271
count mode, selection of ...................................... 264
counter control register H0 (CCRH0) ................... 254
counter control register H1 (CCRH1) ................... 256
counter control register L0/1 (CCRL0/1) .............. 258
counter operation ................................................. 296
counter operation mode ....................................... 312
counter status register 0/1 (CSR0/1) ................... 260
counting pulse width/interval, range for ............... 299
CPU intermittent operation mode................. 129, 136
CPU operation mode ............................................128
CPU specification ...................................................22
current consumption .............................................128
cycle count, execution ..........................................530
D
data count register (DCT) .......................................85
data counter (DCT).................................................75
data polling flag (DQ7), state transitions of ..........478
data register (ADCR2 and ADCR1)......................365
data register (IDAR)..............................................435
dedicated prescaler control register (SDCR)........385
dedicated register ...................................................27
delay interrupt event module, block diagram of......99
delay interrupt event module, list of register in .......99
delay interrupt event module, note on using.........100
delay interrupt event module, operation of ...........100
different mode (S1, S0), setting bit of ...................160
direct addressing ..................................................519
direct page register (DPR)......................................36
divide ratio control register (DIVR0 to DIVR2) ......283
DMA control status register (DMACS)....................76
DMA descriptor.......................................................73
DMA processing procedure ....................................78
DQ3 ......................................................................482
DQ5 ......................................................................481
DQ6 ......................................................................480
DQ7 ......................................................................478
DTP operation ......................................................352
DTP/external interrupt unit operation, procedure for
...................................................................353
DTP/external interrupt unit, block diagram of .......348
DTP/external interrupt unit, list of register ............349
DTP/external interrupt unit, overview of ...............348
E
effective address field...................................518, 533
enable interrupt request register...........................349
end timing of automatic algorithm.........................474
erasing all data in flash memory (chip erase).......487
erasing arbitrary data in flash memory (sector erase)
...................................................................488
event count mode .................................................327
event count mode (external clock mode)..............311
executing undefined instruction, exception
processing interrupt by .................................93
execution cycle count ...........................................530
execution cycle count, calculating ........................531
expanded I/O serial interface, block diagram of ...378
INDEX
575