Fujitsu F2MC-16LX Hardware Manual page 359

I PPG output operation
For the 8/16-bit PPG timer, PPG operation of channel 0 (channel 2 or channel 4) is started by
setting bit 7 of the PPGC0 register (PEN0) to "1". Similarly, PPG operation of channel 1
(channel 3 or channel 5) is started by setting bit 15 of the PPGC1 register (PEN1) to "1" to start
counting. By subsequently setting bit 7 of the PPGC0 (PEN0) or bit 15 of the PPGC1 (PEN1) to
"0", the count operation is stopped, and the pulse output level is fixed at L.
In 8-bit prescaler/8-bit PPG mode, do not set channel 0 (channel 2 or channel 4) to stop mode
and channel 1 (channel 3 or channel 5) to active mode.
In 16-bit PPG mode, use bit 7 of the PPGC0 register (PEN0) and bit 15 of the PPGC1 register
(PEN1) to control simultaneous start or stop of operation.
In the following, the operation for PPG output is described.
During PPG operation, a pulse signal with an arbitrary interval and duty ratio (ratio of "H"-level
pulse width to "L"-level pulse width) is repeatedly output. After it starts to output the pulse signal,
the PPG will not stop until operation stop is specified.
Figure 17.3-1 "Output waveform during PPG output operation" shows the output waveform
during PPG output.
Figure 17.3-1 Output waveform during PPG output operation
PEN
Output pin PPG
Operation start by PEN (from L side)
T × (L + 1) T × (H + 1)
(Start)
CHAPTER 17 8/16-BIT PPG TIMER
L : PRLL value
H : PRLH value
T : peripheral clock
(by PPGC clock selection)
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