Mode Data - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 7 MODE SETTING
7.3

Mode Data

Mode data stored at address "FFFFDF
immediately after the reset sequence. Mode data is read and stored in the CPU
automatically by mode fetching.
I Mode data
During the reset sequence, mode data at address "FFFFDF
CPU core. The CPU uses this mode data to set the memory access mode. The contents of the
mode register can be changed only by the reset sequence. Furthermore, mode data settings
become valid only after the reset sequence. The configuration of mode data is shown in the
figure below.
Mode data
I Setting bits of different modes (S1, S0)
Bits S1 and S0 specify the bus mode and access mode that is set after completion of the reset
sequence.
Table 7.3-1 "Contents of bit S1 and S0 settings" lists the contents of the settings of bits S1 and
S0.
Table 7.3-1 Contents of bit S1 and S0 settings
S1
0
0
1
1
160
" in memory specifies the operation
H
7 6 5
M1 M0 0
Bus mode
setting bits
S2
0 External data bus 8-bit mode
1 External data bus 16-bit mode
0 External data bus 8-bit mode
1 External data bus 16-bit mode
H
4 3 2 1
S1 S0 0 0
Setting bits Function expansion
of different bits
modes (reserved area)
Functions
Address data bus multiplex
Address data bus non-multiplex
" is sent to the mode register in the
0
0