Fujitsu F2MC-16LX Hardware Manual page 86

CHAPTER 3 INTERRUPT
I List of µ µ µ µ DMA registers
❍ DMA enable register (DER)
DMA enable register (DER) has the bit configuration shown in the diagram below.
Bit
0000AD
0000AC
DMA enable register (DER) has the bit functions listed below.
.
ENx bit
0
(Initial value)
1
❍ DMA stop status register (DSSR)
The bit configuration of the DMA stop status register (DSSR) is shown below.
Bit
0000A4
The function of each bit in the DMA stop status register (DSSR) is shown below.
STPx bit
0
(Initial value)
1
70
15 14 13
EN15 EN14 EN13
R/W R/W R/W
7 6 5
EN7 EN6 EN5
R/W R/W R/W
Outputs an interrupt request from a resource to the interrupt controller.
(An interrupt request from a resource is not used as a DMA start request).
An interrupt request output from a resource is used as a DMA start request.
Cleared to "0" when the DMA transfer byte count reaches 0.
7 6 5
STP7 STP6 STP5
H
R/W R/W R/W
No STOP request is accepted in a DMA transfer.
STOP request is accepted in a DMA transfer to stop DMA operation.
STOP request is accepted only the UART receive (channels 7).
The bits other than the bit 7 are not valid.
Writing "1" by running software is not valid.
12 11 10 9
EN12 EN11 EN10 EN9
R/W R/W R/W R/W
4 3 2 1
EN4 EN3 EN2 EN1
R/W R/W R/W R/W
Function
4 3 2 1
STP4 STP3 STP2 STP1
R/W R/W R/W R/W
Function
8
EN8 DERH
Initial value 00000000
R/W
0
EN0 DERL
Initial value 00000000
R/W
0
STP0 DSSR
Initial value 00000000
R/W
B
B
B