Fujitsu F2MC-16LX Hardware Manual page 135

Table 5.3-1 Functions of bits in clock selection register (CKSCR)
Bit name
SCM:
Bit 15
Sub-clock display bit
MCM:
Bit 14
PLL clock display bit
WS1, WS0:
Bit 13
Oscillation stabilization
Bit 12
wait time selection bits
SCS:
Bit 11
Sub-clock selection bit
• This bit displays whether the main clock or sub-clock is selected as a
machine clock.
• If the bit is "0", the sub-clock is selected. If "1", the main clock or PLL
clock is selected.
• If SCS = 1 and SCM = 0, the mode is the waiting time for stable
oscillation of the main clock.
• This bit displays whether the main clock or PLL clock is selected as a
machine clock.
• If this bit is "0", the PLL clock is selected. If "1", the main clock or sub-
clock is selected.
• If PLL clock selection bit (MCS) = 0 and MCM = 1, the mode is the
waiting time for stable oscillation of the PLL clock.
• Selects the waiting time for stable oscillation of oscillation clock in a
change from the sub-clock mode to the main clock mode or from the
sub-clock mode to the PLL clock mode if the stop mode is canceled.
• Initialized to "11 " by all reset factors.
B
Note:
The specified value for the waiting time for stable oscillation must be
suitable for the oscillator used. Refer to Section 4.2 "Reset Factors
and Waiting time to Stable Oscillation", for more information. Specify
"00 " only if the mode is the main clock mode.
B
When the main clock is switched to PLL clock mode, the PLL clock
oscillation stabilization wait time is fixed at 2
mode is switched to PLL clock mode or when PLL stop mode is
returned to PLL clock mode, the oscillation stabilization wait time uses
the specified values in the WS1 and WS0 bits. For PLL oscillation
stabilization, at least 2
clock mode is switched to PLL clock mode, or when PLL clock mode is
switched to PLL stop mode, set WS1 and WS0 bits to "10
• This bit specifies selection of the main clock or sub-clock as a machine
clock.
• If this bit is "0", the sub-clock is selected. If "1", the main clock is
selected.
• When this bit is rewritten from "1" to "0", the mode is switched to the
sub-clock mode synchronizing the sub-clock (approx. 130µs.)
• Writing "1" when this bit is "0" generates a standby period for stable
oscillation of the main clock. The timebase timer is automatically
cleared.
• Use the sub-clock as an operation clock when the sub-clock is
selected. (The machine clock changes to a frequency of 8 kHz during
low-speed oscillation at 32 kHz)
• If both SCS and MCS are "0", SCS is assigned with priority, and the
sub-clock is selected.
• Initialized to "1" by all reset factors.
Function
14
/HCLK. When sub-clock
14
/HCLK is required. Accordingly, when sub-
CHAPTER 5 CLOCKS
" or "11 ".
B B
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