Fujitsu F2MC-16LX Hardware Manual page 526

APPENDIX
Table A-2 I/O Map (Continued)
Address
75
H
76
H
PWC0 control status register
77
H
78
H
PWC0 data buffer register
79
H
7A
H
PWC1 control status register
7B
H
7C
H
PWC1 data buffer register
7D
H
7E
H
PWC2 control status register
7F
H
80
H
PWC2 data buffer register
81
H
82 PWC0 divide ratio register
H
83
H
84 PWC1 divide ratio register
H
85
H
86 PWC2 divide ratio register
H
87
H
2
88 I C bus status register
H
2
89 I C bus control register
H
2
8A I C bus clock select register
H
2
8B I C bus address register
H
2
8C I C bus data register
H
8D
H
µPG status register
8E
H
8F to
H
9B
H
µDMA status register
9C
H
µDMA status register
9D
H
9E
H
510
Register Abbreviation Access
Reserved area
PWCSR0 R/W
PWCR0 R/W
PWCSR1 R/W
PWCR1 R/W
PWCSR2 R/W
PWCR2 R/W
DIVR0 R/W
Reserved area
DIVR1 R/W
Reserved area
DIVR2 R/W
Reserved area
IBSR R
IBCR R/W
ICCR R/W
IADR R/W
IDAR R/W
Reserved area
PGCSR R/W
Use prohibited
DSRL R/W
DSRH R/W
Use prohibited
Resource Initial value
00000000
0000000X
16-bit PWC timer
(ch0)
00000000
00000000
00000000
0000000X
16-bit PWC timer
(ch1)
00000000
00000000
00000000
0000000X
16-bit PWC timer
(ch2)
00000000
00000000
PWC (ch0) ------00
PWC (ch1) ------00
PWC (ch2) ------00
00000000
00000000
2
I C --0XXXXX
-XXXXXXX
XXXXXXXX
µPG
0000----
µDMA
00000000
µDMA
00000000