Ppg1 Operation Mode Control Register (Ppgc1) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 12 8/16-BIT PPG

12.3.2 PPG1 Operation Mode Control Register (PPGC1)

The PPG1 operation mode control register (PPGC1) is used for selection of the
operation mode of the 8/16-bit PPG, pin output control, count clock selection, and
trigger control.
Here, ch.1 is used as an example. For ch.2 and ch.4, replace ch.0 in the explanation
with ch.2 or ch.4. For ch.3 and ch.5 replace ch.1 in the explanation with ch.3 or ch.5.
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 12.3-3 PPG1 Operation Mode Control Register (PPGC1)
PPG1 operation mode
control register
Address :ch.1 000045
H
ch.3 00004D
H
ch.5 000055
H
Read/write
Initial value
[bit15] PEN1 (Ppg ENable)
The PEN1 bit selects the start of PPG operation and the operation mode of the PPG as
shown in Table 12.3-5. Writing "1" to this bit causes the PPG to start counting.
Table 12.3-5 Operation Enable Bit (PEN1) Function
PEN1
0
1
[bit13] POE1 (Ppg Output Enable)
The POE1 bit controls the pulse output external pin PPG1 as shown in Table 12.3-6.
Table 12.3-6 POE1 (PPG1 Pin Output Enable Bit) Function
POE1
0
1
200
15 14 13
bit
PENx POEx PIEx
(R/W) (-) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (-) (0) (0)
Operation stopped (low level held output) [initial value]
PPG operation enabled
General-purpose port pin (pulse output disabled) [initial value]
PPG1 serving as a pulse output pin (pulse output enabled)
12 11 10 9
PUFx MD1 MD0
Reserved
(-)
(0) (0) (0) (1)
Function
Function
8
PPGC
x=1,3,5