Overview - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER

12.1 Overview

The 16-bit input/output timer consists of one module of a 16-bit free-running timer, six
modules of output compare and two modules of input capture. This function provides
an output of six independent waveforms based on the 16-bit free-running time,
enabling measurement of input pulse widths and external clock intervals.
I Configuration and function of 16-bit input/output timer
The 16-bit input/output timer consists of a 16-bit free-running timer, output compare and input
capture, whose functions are explained below.
❍ 16-bit free-running timer (x 1)
16-bit free-running timer consists of 16-bit up-counter, control register and prescaler. The output
of this timer counter is used as a base time (timebase timer) of input capture and output
compare. The clock used for counter operation is selected from 8 types. (φ: machine clock)
Internal clock: 8 types (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128)
•
• The basic machine clock is selected from either an internal clock or external clock (FRCK).
An interrupt is generated in the event of a counter overflow or a compare match between the
output and the compare clear register (the compare match requires mode setting).
The count value can be initialized to "0000
compare match with compare clear register 0.
❍ Output compare (x 6)
Output compare consists of three 16-bit compare registers, a compare output latch, and a
control register. If a 16-bit free-running timer and compare register have matching values, the
output level is reversed with a generation of an interrupt.
• Six compare registers operate independently. Each compare register has a corresponding
output pin and interrupt flag.
• Two compare registers are used as a pair to control the output pin.
• Sets the output pin to its initial value.
• An interrupt is generated by a compare match.
❍ Input capture (x 2)
Input capture consists of two independent external input pins and corresponding capture
registers and control registers. If an edge of a signal input from the external input pin is
detected, the 16-bit free-running timer value is specified in the capture register and, at the same
time, an interrupt is generated.
• The edge of an external input signal can be selected from its rising edge and falling edge.
• The two input capture operate independently.
Interrupts occur at the valid edge of external input signals. Input capture can start DMAC by the
interrupt.
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" in the event of a reset, clearing by software, or
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