Fujitsu F2MC-16LX Hardware Manual page 186

CHAPTER 7 MODE SETTING
[Bit 12] IOBS
This bit specifies the bus width for accessing external buses corresponding to areas in a
range of 0000D0
0
1
[Bit 11] HMBS
This bit specifies the bus width for accessing external buses corresponding to areas in a
range of 800000
0
1
[Bit 10] WRE
This bit controls the output of external write signals (both the WRH and WRL pins in the
external data bus 16-bit mode or the WRL pin in the external data bus 8-bit mode).
0
1
[Bit 9] LMBS
This bit specifies the bus width for accessing external buses corresponding to areas in a
range of 002000
0
1
Note:
To permit use of the WRH or WRL function by using the WRE bit in the external data bus 16-
bit mode, set P53 and P52 to the input mode (set bits 3 and 2 of DDR5 to "0").
Furthermore, even when RDY and HRQ input is permitted by RYE and HDE bits, the I/O port
function of a port is enabled. Therefore, be sure to set "0" (input mode) to the bit in DDR5
corresponding to that port.
170
to 0000FF
H H
16-bit bus width access [Initial value]
8-bit bus width access
to FFFFFF
H H
16-bit bus width access
[Default value in external vector mode 1]
8-bit bus width access
[Default value in external vector modes 0 and 2]
I/O port (P53, P52) operation (write signal output prohibited)
Write strobe signal (WRH and WRL, or only WRL) output permitted [Initial value]
to 7FFFFF
H H
16-bit bus width access [Initial value]
8-bit bus width access
, in the external data bus 16-bit mode.
, in the external data bus 16-bit mode.
, in the external data bus 16-bit mode.