Port Registers (Pdr0 To Pdra) - Fujitsu F2MC-16LX Hardware Manual

Mb90470 series 16-bit microcontroller

Hide thumbs Also See for F2MC-16LX:

Table of Contents

CHAPTER 8 I/O PORT

Port registers (PDR0 to PDRA)

This section shows the configuration and explains the functions of port registers

(PDR0 to PDRA)

I Port registers (PDR0 to PDRA)

Figure 8.2-1 "Port registers (PDR0 to PDRA)" shows a list of port registers (PDR0 to PDRA).

Address:000000

Address:000001

Address:000002

Address:000003

Address:000004

Address:000005

Address:000006

Address:000007

Address:000008

Address:000009

Address:00000A

R/W access to I/O ports differs slightly in operation from R/W access to memory.

Be careful about such R/W access because it operates as follows:

During reading: The level of the relevant pins is read and output.

During writing: Writing is performed on the latch for output.

During reading: The value of the data register latch is read and output.

During writing: Output is to the relevant pins.

Figure 8.2-1 Port registers (PDR0 to PDRA)

P70 11XXXXXX R/W (Note)

Initial value