Fujitsu F2MC-16LX Hardware Manual page 87

❍ DMA status register (DSR)
The bit configuration of the DMA status register (DSR) is shown below.
15
Bit
00009D DE15
H
R/W
Bit
7
00009C
DE7
H
R/W
The functions of each bit in the DMA status register (DSR) is shown in the table below.
DEx bit
0
No DMA transfer has ended.
(Initial value)
If a DMA transfer ends, an interrupt request is output to the interrupt
1
controller.
Note: If "1" is written, DMA transfer does not end. An interrupt is output to the interrupt
controller.
14 13 12 11
DE14 DE13 DE12 DE11
R/W R/W R/W R/W
6 5 4
DE6 DE5 DE4 DE3
R/W R/W R/W R/W
CHAPTER 3 INTERRUPT
10 9 8
DE10 DE9 DE8
R/W R/W R/W
3 2 1 0
DE2 DE1 DE0
R/W R/W R/W
Function
DSRH
Initial value 00000000
B
DSRL
Initial value 00000000
B
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