Fujitsu F2MC-16LX Hardware Manual page 362

CHAPTER 17 8/16-BIT PPG TIMER
I Initial value of hardware components
The hardware components of the 8/16-bit PPG timer are initialized to the following values at
reset.
Hardware components other than above mentioned are not initialized.
I Write timing to the reload register
It is recommended that word transfer instructions be used for writing data to the reload registers
PRLL and PRLH in modes other than 16-bit PPG mode. Writing data to the register two times
by separate byte transfer instructions may result in an unexpected output pulse width,
depending on the timing.
Figure 17.3-3 "Timing chart of writing to the reload register" shows the timing for writing to the
reload register.
PPG0
In Figure 17.3-3 "Timing chart of writing to the reload register", PRLL is changed from A to C
before (1), and the PRLH value is changed from B to D after (1). However, since the PRL values
at (1) are PRLL = C and PRLH = B, the pulses for the L-side count of C and the H-side count of
B are generated only once. Similarly, to write data to the PRL of channels 0/2/4 and channels 1/
3/5, use a long word transfer instruction or use a word transfer instruction in the order channel 0
--> channel 1 (respectively channel 2 --> channel 3, channel 4 --> channel 5). In this mode, data
is temporarily written from channels 0/2/4 to the PRL; when data is then written from channels 1/
3/5 to the PRL, it is actually written to the PRL of channel 0/2/4.
In modes other than 16-bit PPG mode, writing to channel 0/2/4 and channel 1/3/5 are performed
independently.
Figure 17.3-4 "Flowchart of the PRL write operation" shows a flowchart of the PRL write
operation.
Write data for PRL of ch0
Writing from ch0 in
a mode other than
16-bit PPG mode
346
< Registers >
< pulse output >
< interrupt request unit >
Figure 17.3-3 Timing chart of writing to the reload register
A B A
Figure 17.3-4 Flowchart of the PRL write operation
Temporary latch
PRL of ch0
→
PPG0 0X000001
→
PPG1 00000001
→
PPG01 XXXXXX00
→
PPG0 "L"
→
PPG1 "L"
→
PE0 Output prohibited
→
PE1 Output prohibited
→
IRQ0 "L"
→
IRQ1 "L"
B C B C D
(1)
Write data for PRL of ch1
Writing from ch1 in
a mode other than
16-bit PPG mode
C D
Write data for ch1
PRL of ch1