Ppg1/Ppg3 Operation Mode Control Register (Ppgc1/Ppgc3) - Fujitsu MB90335 Series Hardware Manual

CHAPTER 15 8/16-BIT PPG TIMER
15.2 Registers of 8/16-bit PPG Timer
15.2.2 PPG1/PPG3 Operation Mode Control Register
(PPGC1/PPGC3)
Configuration and functions of PPG1/PPG3 operation mode control register (PPGC1/
PPGC3) are described.

■ PPG1/PPG3 Operation Mode Control Register (PPGC1/PPGC3)

The PPG1/PPG3 operation mode control register (PPGC1/PPGC3) selects the operation mode of ch.1/ch.3,
controls the pin output, selects the count clock, and controls the trigger.
Figure 15.2-3 shows the bit configuration of PPG1/PPG3 operation mode control registers (PPGC1/
PPGC3).
Figure 15.2-3 Bit Configuration of PPG1/PPG3 Operation Mode Control Registers (PPGC1/PPGC3)
bit
ch.1 : 000047
H
ch.3 : 000049
H
R/W : Readable/Writable
- : Undefined
X : Undefined value
The following describes functions of each bit of PPG1/PPG3 operation mode control registers (PPGC1/
PPGC3):
[bit15] PEN1: ppg Enable (operation permission)
The operation start and operation mode of PPG1/PPG3 are selected.
PEN1
0
1
• When this bit is set to "1", PPG count starts.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit14] Undefined bit
The read value is undefined. Nothing is affected when it is written.
346
15 14 13 12
PEN1 PE10 PIE1 PUF1
(R/W) (R/W) (R/W) (R/W)
(0) (X) (0) (0)
FUJITSU MICROELECTRONICS LIMITED
11 10 9 8
MD1 MD0
Reserved
(R/W) (R/W) (R/W)
(0) (0) (0) (1)
Operating State
Operation stop ("L" level power output maintenance)
PPG Enabling Operations
MB90335 Series
PPGC1/PPGC3
PPG Operation mode control register
Read/Write
Initial value
CM44-10137-6E