Fujitsu F2MC-16LX Hardware Manual page 407

❍ Instruction shift in external shift clock mode (LSB first)
During instruction shift, "H" will be output if the PDR bit corresponding to SCK is set to "1" and
"L" will be output if the bit is set to "0". (If SCOE = 0 when external shift clock mode is selected.)
SCK1,2
STRT
BUSY
SOT1,2
❍ Stop by STOP = 1 (LSB first, internal clock used)
SCK1,2
(Transfer start)
STRT
BUSY
STOP
SOT1,2
I Operation during serial data transfer
During serial data transfer, data from the serial output pin (SOT2) is output at a falling edge of
the shift clock. Data from the serial input pin (SIN) is input at a rising edge.
❍ LSB first (if the BDS bit is "0")
SCK1,2
SIN1,2
SOT1,2
❍ MSB first (If the BDS bit is "1")
SCK1,2
SIN1,2
SOT1,2
Figure 20.3-5 Instruction shift in external shift clock mode
PDR SCK bit "0"
If MODE = 0
DO6
Figure 20.3-6 Stop timing when the STOP bit is set to "1"
If MODE = 0
DO3
Figure 20.3-7 Input and output shift timing (LSB first)
DI0 DI1 DI2
SOT output
DO0 DO1 DO2
Figure 20.3-8 Input and output shift timing (MSB first)
DI7 DI6 DI5
SOT output
DO7 DO6 DO5
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE
PDR SCK bit "0"
PDR SCK bit "1"
(Transfer end)
DO7 (Data hold)
(Transfer end)
DO4
DO5 (Data hold)
SIN input
DI3 DI4 DI5
DO3 DO4 DO5
SIN input
DI4 DI3 DI2
DO4 DO3 DO2
Output of "1"
DI6 DI7
DO6 DO7
DI1 DI0
DO1 DO0
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