Fujitsu F2MC-16LX Hardware Manual page 136

CHAPTER 5 CLOCKS
Table 5.3-1 Functions of bits in clock selection register (CKSCR) (Continued)
Bit name
MCS:
Bit 10
PLL clock selection bit
CS1, CS0:
Bit 9
Multiplication rate
Bit 8
selection bit
HCLK: Oscillation clock
120
• This bit specifies selection of the main clock or PLL clock as a machine
clock.
• If this bit is "0", the PLL clock is selected. If "1", the main clock is
selected.
• Writing "0" when this bit is "1" generates a waiting time for stable
oscillation of the PLL clock. The timebase timer is automatically
cleared. The interrupt request flag bit (TBOF) of the timebase timer
control register (TBTC) is also cleared.
• When the main clock is switched to PLL clock mode, the oscillation
stabilization wait time is fixed at 2
wait time is about 4.1 ms if the oscillation clock has a frequency of 4
MHz.) When sub-clock mode is switched to PLL clock, the oscillation
stabilization wait time uses the specified values in the oscillation
stabilization wait time selection bits (CKSCR: WS1, WS0).
• When the main clock is selected, the operation clock is the oscillation
clock divided by 2. (The operation clock is 2 MHz if the oscillation clock
is 4 MHz.)
• Initialized to "1" by all reset factors.
Note:
When writing "0" when the MCS bit is "1", write while the timebase
timer interrupt is masked by using the interrupt request enable bit
(TBIE) of the TBTC register or the interrupt level register (ILM).
• This bit selects the multiplication rate of the PLL clocks.
• Selection is from four multiplication rates.
• All reset factors initialize it to "00B".
Note:
Writing is disabled if the MCS bit or MCM bit is "0". Rewrite the CS1
and CS0 bits after setting the MCS bit to "1" (main clock mode).
Function
14
/HCLK. (The oscillation stabilization