Block Diagram Of Mb90470 - Fujitsu F2MC-16LX Hardware Manual

Mb90470 series 16-bit microcontroller
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1.2

Block Diagram of MB90470

This section has a block diagram of the MB90470.
I Block diagram of MB90470
Figure 1.2-1 "Block diagram of MB90470" is a block diagram of the MB90470.
X0,X1,RST
Clock control
8
X0A,X1A
MD2,MD1,MD0
µDMA
Communication
SIN0
SOT0
SCK0
SIN1,2
I/O extensive
SOT1,2
serial interface
× 2 channels
SCK1,2
AV
CC
AVRH
A/D converter
AV
SS
ADTG
AN0-7
PWC0
PWC1
PWC2
8
P00
P07
P00 to P07(×8) : With register for input pull-up resistor settings
P10 to P17(×8) : With register for input pull-up resistor settings
P40 to P47(×8) : With register for open drain settings
P70 to P75(×6) : Open drain with register
P76, 77(×2)
Note:
In the Figure 1.2-1 "Block diagram of MB90470", the I/O port shares a pin with each built-in
function block. The pin cannot be used as an I/O port if it is used as a built-in module pin.
Figure 1.2-1 Block diagram of MB90470
circuit
FMC16LX-series core
RAM
ROM
prescaler
2
UART
(10 bits)
16-bit PWC
× 3 channels
8
8
8
8
P10
P20
P30
P40
P17
P27
P37
P47
: Open drain
CHAPTER 1 OVERVIEW OF MB90470
CPU
Interrupt
controller
8/16-bit PPG
8/16-bit U/D
Chip select
Input/output timer
16-bit input capture × 2
16-bit output compare × 6
16-bit free-running timer
16-bit reload timer
IIC interface
External
interrupt
I/O port
8
8
8
8
P50
P60
P70
P80
P57
P67
P77
P87
PPG0,1
PPG2,3
PPG4,5
AIN0,1
BIN0,1
counter
ZIN0,1
EXTC
µPG
MT00
MT01
CS0,1,2,3
IN0,1
OUT0,1,2,3,4,5
TIN0
TOT0
SCL
SDA
8
IRQ0-7
8
4
P90
PA0
P97
PA3
5

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