Fujitsu F2MC-16LX Hardware Manual page 75

I Hardware interrupt operation
Figure 3.4-2 "Hardware interrupt operation" shows the operation from the generation of
hardware interrupt until the completion of interrupt processing.
Internal data bus
(7)
(8)
IL : Interrupt level setting bit for interrupt control register (ICR)
PS : Processor status
I : Interrupt enable flag
ILM : Interrupt level mask register
IR : Instruction register
FF : Flip-flop
1. An interrupt factor is generated in the peripheral function.
2. If an interrupt is permitted after referring to the interrupt enable bit of the peripheral function,
the interrupt request is issued from the peripheral to the interrupt controller.
3. The interrupt controller that receives the interrupt request also checks the priority of a
requested interrupt, and it then transfers the interrupt level (IL) corresponding to the interrupt
request to the CPU.
4. The CPU compares the interrupt level (IL) requested from the interrupt controller with the
interrupt level mask register (ILM).
5. If the compare results have a priority higher than the current interrupt processing level, the I-
flag of the condition code register (CCR) is checked.
6. As a result of the check in step 5, if the I-flag indicates an interrupt enable (I = 1), the
interrupt operation waits until the instruction currently being executed is completed and then
sets ILM to the requested level (IL).
7. The contents of the resisters are stored and branched to the interrupt processing routine.
8. Software in the user's interrupt processing routine clears the interrupt factor generated in
step 1 for executing the RETI instruction, and then interrupt processing is completed.
Figure 3.4-2 Hardware interrupt operation
PS,PC
Microcode
2
F MC-16LX CPU
Other peripheral
function
Peripheral function generating
an interrupt request
Enable FF
AND
Factor FF
(1)
RAM
PS II
IR
Check
(6)
(5)
comparator
(2)
CHAPTER 3 INTERRUPT
LM
Comparator
(4)
(3)
Level
Interrupt
level IL
Interrupt controller
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