Fujitsu F2MC-16LX Hardware Manual page 267

• An interrupt occurs when the count direction is switched
I Block diagram of 8/16-bit up/down counter/timer
Figure 13.1-1 "Block diagram of 8/16-bit up/down counter/timer (channel 0)" and Figure 13.1-2
"Block diagram of 8/16-bit up/down counter/timer (channel 1)" are block diagrams of the 8/16-bit
up/down counter/timer.
Figure 13.1-1 Block diagram of 8/16-bit up/down counter/timer (channel 0)
CGE1
Edge/level
ZIN0
detected
AIN0
Up/down count
clock selection
BIN0
Prescaler
CLKS
CGE0 CGSC
UDCC
CES1 CES0
CMS1 CMS0
UDMS
UDF1 UDF0 CDCF CFIE
CSTR
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
Data bus
8 bits
RCR0 (reload/compare register 0)
Reload
CTUT
control
UCRE
RLDE
Counter clear
8 bits
UDCR0 (up/down count register 0)
Count clock
CITE UDIE
Interrupt
output
Carry
CMPF
UDFF OVFF
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