Fujitsu F2MC-16LX Hardware Manual page 419

0 No reception data
1 Reception data loaded
[Bit 11] TDRE: Transmitter Data Register Empty
This bit acts as an interrupt request flag that indicates that transmission data can be written
to the SODR register. This flag is cleared when transmission data is written to the SODR
register. The flag will be set again reset to indicate that the next item of transmission data
can be written as soon as written data has been loaded into the transmission shift unit and
data transfer starts.
0 Prohibit writing of transmission data
1 Allow writing of transmission data
[Bit 10] BDS
This bit is used to control the selection of a data transfer direction.
0 Serial data is transferred starting with the LSB side. (LSB first)
1 Serial data is transferred starting with the MSB side. (MSB first)
Note:
When this bit is rewritten after writing data to the SDR register to switch between the upper
side and lower side of data, the data in the serial status register becomes invalid in read and
write operations.
[Bit 9] RIE: Receiver Interrupt Enable
This bit controls reception interrupts.
0 Prohibit interrupts.
1 Allow interrupts.
In addition to PE, ORE, and FRE errors, normal reception by RDRF also acts as reception
interrupt source.
[Bit 8] TIE: Transmitter Interrupt Enable
This bit controls send interrupts.
0 Prohibit interrupts.
1 Allow interrupts.
Note:
If transmission operation becomes disabled during transmission, the transmission operation
stops after no more data remains in the transmission data buffer (SODR1). For writing "0",
wait a predefined time after data has been written to SODR1. In clock asynchronous transfer
mode, the term "predefined time" means 1/16 the time corresponding to the baud rate using
in clock asynchronous transfer mode. In clock synchronous transfer mode, this term refers to
the time corresponding to the baud rate.
CHAPTER 21 UART
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