Fujitsu F2MC-16LX Hardware Manual page 527

Table A-2 I/O Map (Continued)
Address
Delay interrupt source generate/
9F
H
A0 Power saving mode register
H
A1 Clock select register
H
A2 to
H
A3
H
µDMA stop status register
A4
H
Automatic ready function selection
A5
H
External address signal control
A6
H
A7 Bus control signal control register
H
A8 Watchdog control register
H
A9 Timebase timer control register
H
AA Watch timer control register
H
AB
H
µDMA control register
AC
H
µDMA control register
AD
H
AE Flash memory control status register
H
AF
H
B0 Interrupt control register 00
H
B1 Interrupt control register 01
H
B2 Interrupt control register 02
H
B3 Interrupt control register 03
H
B4 Interrupt control register 04
H
B5 Interrupt control register 05
H
B6 Interrupt control register 06
H
B7 Interrupt control register 07
H
B8 Interrupt control register 08
H
B9 Interrupt control register 09
H
BA Interrupt control register 10
H
BB Interrupt control register 11
H
BC Interrupt control register 12
H
Register
delete register
register
register
Abbreviation Access
DIRR R/W
LPMCR R/W
CKSCR R/W
Reserved area
DSSR R/W
ARSR W
HACR W
EPSR W
WDTC R/W
TBTC R/W
WTC R/W
Reserved area
DERL R/W
DERH R/W
FMCR R/W
Use prohibited
ICR00 R/W
ICR01 R/W
ICR02 R/W
ICR03 R/W
ICR04 R/W
ICR05 R/W
ICR06 R/W
ICR07 R/W
ICR08 R/W
ICR09 R/W
ICR10 R/W
ICR11 R/W
ICR12 R/W
APPENDIX A Memory Map
Resource Initial value
Delay interrupt
-------0
generate module
Saving power 00011000
Saving power 11111100
µDMA
00000000
External pin 0011--00
External pin 00000000
External pin 1000*10-
Watchdog timer XXXXX111
Timebase timer 1XX00100
Watch timer 10001000
µDMA
00000000
µDMA
00000000
Flash memory I/F 000X0000
XXXX0111
XXXX0111
XXXX0111
XXXX0111
XXXX0111
XXXX0111
Interrupt controller XXXX0111
XXXX0111
XXXX0111
XXXX0111
XXXX0111
XXXX0111
XXXX0111
511