Fujitsu F2MC-16LX Hardware Manual page 177

I Bus mode setting bits (M1, M0)
Bits M1 and M0 specify the operation mode that is set after completion of the reset sequence.
Table 7.3-2 "Contents of bit M1 and M0 settings" lists the contents of the settings of bits M1 and
M0.
Table 7.3-2 Contents of bit M1 and M0 settings
M1
0
0
1
1
Figure 7.3-1 "Relationship between access areas and physical addresses" shows the
correspondence between access areas and physical addresses.
Figure 7.3-1 Relationship between access areas and physical addresses
FFFFFF
H
Address #1
FC0000
H
010000
H
Address #2
Address #3
000100
H
0000D0
H
000000
H
Note:
"Address #X" is determined based on individual models. See Appendix A "Memory Map", for
details.
M0
0 Single-chip mode
1 Internal ROM and external bus mode
0 External ROM and external bus mode
1 (Setting is prohibited)
Single chip
ROM area
ROM area,
image of FF bank
RAM Register
Peripheral
Internal access
Functions
Internal ROM
external bus
ROM area
ROM area,
image of FF bank
RAM Register
Peripheral
External access
CHAPTER 7 MODE SETTING
External ROM
external bus
RAM Register
Peripheral
No access
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