Fujitsu F2MC-16LX Hardware Manual page 351

[Bit 4] PIE0:ppg Interrupt enable (PPG interrupt enable)
This bit is used to allow or prohibit PPG interrupts.
PIE0
0 Interrupts prohibited
1 Interrupts allowed
• If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is
"0", no interrupts are generated.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[Bit 3] PUF0: ppg Underflow Flag (PPG counter underflow)
This bit indicates the result of a PPG counter underflow detection.
PUF0
0 No PPG counter underflow detected
1 PPG counter underflow detected
In 8-bit PPG6 channel mode (PPG0/1,PPG2/3,PPG4/5) and 8-bit prescaler/8- bit PPG mode,
this bit is set to "1" if an underflow occurs because the counter value for channel 0/2/4 changes
from 00 to FF . In 16-bit PPG3 channel mode (PPG0/PPG1, PPG2/PPG3, PPG4/PPG5), this
H H
bit is set to "1" if the counter value of channel 1, 3, 5 or channel 0, 2, 4 changes from 0000
FFFF . Writing "0" clears this bit to "0". Writing "1" has no effect. Read-modify-write type
H
instructions always return "1".
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[Bit 0] reserved bit
This bit is reserved. When setting PPGC0, always set this bit to "1".
Operation state
Operation state
CHAPTER 17 8/16-BIT PPG TIMER
to
H
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