Fujitsu F2MC-16LX Hardware Manual page 166

CHAPTER 6 LOW-POWER CONSUMPTION MODE
Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode
Table 6.7-3 "Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus
mode" lists pin states in the external bus 8-bit data bus mode and multiplex 6-bit external bus
mode.
Table 6.7-3 Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode
Pin name In sleep state
P07 to P00 Input disabled/
(AD07 to AD00) Output Hi-Z
P17 to P10 Output state
(AD15 to AD08) (*1)
P27 to P20 Output state
(A23 to A16) (*1, *4)
Input disabled/
P57 (CLK) Output enabled
(*2, *4)
P56 (RDY)
P55 (HAK)
Maintains the
previous state
P54 (HRQ)
(*5)
P53 (WRH)
P52 (WRL) "H" output (*5)
P51 (RD) "H" output
P50 (ALE) "L" output
P37 to P30
P47 to P40
P67 to P60
Maintains the
P77 to P70 previous state
(*5)
P97 to P91
PA3 to PA0
P90 (CS0)
Input enabled
P87 to P80
(*3)
*1: "Output state" means that the pin-drive transistors are set in a drive-enabled state, but internal circuits are stopped so that a fixed value, "H" or "L", is
output. When internal peripheral circuits are in operation and output functions are used, output varies except when reset. Output does not vary during a
reset.
*2: "Output enabled" means that the pin-drive transistors are set in a drive state and that internal circuit operations are enabled. Operational states therefore
are conveyed on the pins.
*3: Same as in other ports when used in the output state. "Input enabled" means that input functions are ready and require pull up/pull down or external input.
*4: The previous values are retained if used as an output port.
*5: The state output immediately before this mode was set is output as is. If it is input, input is disabled.
"Input disabled" means that operations of input gates located very close to the pins are enabled, but pin states cannot be accepted in internal operations
because internal circuits are not operating.
*6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are
disabled and the pins are set to the high-impedance state.
150
When stopped
In hold state
SPL = 0 SPL = 1
Input cutoff/
Output Hi-Z
Input disabled/
Output state
(*1)
Output state Input disabled/
(*1, *4) Output Hi-Z (*4)
Input disabled/ Input disabled/
Output state Output enabled
(*1, *4)
Input disabled
Input cutoff/
Maintains the
previous state
(*5)
Maintains the
Input cutoff/
previous state
Output Hi-Z
(*6)
Input disabled/
"H" output (*5)
Output Hi-Z (*4)
"H" output
Input disabled/
"L" output
Input cutoff/
Maintains the
previous state
Maintains the
(*5) previous state
Input enabled Input enabled
(*3) (*3)
Internal ROM access
When reset
Input disabled/
Output Hi-Z
Output Hi-Z
Output state
(*1)
Input disabled/
Output enabled
(*2, *4) (*2)
(*4)
"L" output
Input disabled/
"I" input Output Hi-Z
(*5)
"H" output
Output Hi-Z
"L" output
Input disabled/
Output Hi-Z
(*5)
"H" output
Input disabled
Internal ROM access
immediately after after external ROM
reset cancellation access
Output Hi-Z/ Output Hi-Z/
Input enabled Input enabled
Maintains the
Output state (*1)
previous address
CLK output CLK output
Output Hi-Z/ Output Hi-Z/
Input enabled Input enable
"H" output "H" output
"L" output "L" output
Output Hi-Z/ Output Hi-Z/
Input enabled Input enabled