Fujitsu F2MC-16LX Hardware Manual page 139

Figure 5.4-1 State transition diagram of machine clock selection
(8)
Main
MCS=1
MCM=1
(1)
SCS=1
SCM=1
CS1,CS0=xx
Main→PLLx
MCS=0
MCM=1
SCS=1
SCM=1
CS1,CS0=xx
PLL1→Main
(7)
MCS=1
MCM=0
SCS=1
SCM=1
CS1,CS0=00
PLL2→Main
MCS=1
(7)
MCM=0
SCS=1
SCM=1
CS1,CS0=01
PLL3→Main
MCS=1
(7)
MCM=0
SCS=1
SCM=1
CS1,CS0=10
PLL4→Main
(7)
MCS=1
MCM=0
SCS=1
SCM=1
CS1,CS0=11
(1) MCS bit "0" write
(2) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 00
(3) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 01
(4) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 10
Main→Sub
MCS=1
MCM=1
SCS=0
(10)
SCM=1
CS1,CS0=xx
Sub→Main
(11)
MCS=1
MCM=1
SCS=1
(6)
SCM=0
CS1,CS0=xx
(2)
(3)
(4)
(5)
PLL multiplied
by one
MCS=0
MCM=0
(6)
SCS=1
SCM=1
CS1,CS0=00
PLL multiplied
by two
MCS=0
MCM=0
(6)
SCS=1
SCM=1
CS1,CS0=01
PLL multiplied
by three
MCS=0
MCM=0
(6)
SCS=1
SCM=1
CS1,CS0=10
PLL multiplied
by four
MCS=0
MCM=0
(6)
SCS=1
SCM=1
CS1,CS0=11
(9)
(16)
(10)
(8)
(8)
Sub→PLL
(12)
MCS=0
(13)
MCM=1
(14)
SCS=1
(15)
SCM=0
CS1,CS0=xx
PLL1→Sub
MCS=1
(17)
MCM=0
SCS=0
(8)
SCM=1
CS1,CS=00
PLL2→Sub
MCS=1
MCM=0
(17)
SCS=0
(8)
SCM=1
CS1,CS0=01
PLL3→Sub
MCS=1
(17)
MCM=0
SCS=0
(8)
SCM=1
CS1,CS0=10
PLL4→Sub
MCS=1
(17)
MCM=0
SCS=0
(8)
SCM=1
CS1,CS0=11
CHAPTER 5 CLOCKS
Sub
MCS=1
MCM=1
SCS=0
SCM=0
CS1,CS0=xx
123