Fujitsu F2MC-16LX Hardware Manual page 88

CHAPTER 3 INTERRUPT
I µ µ µ µ DMA operations
Figure 3.6-1 "µDMA operations" shows µDMA operations.
performed as described below.
1. A peripheral resource (I/O) requests a DMA transfer.
2. The DMA controller reads a descriptor.
3. The transfer source, transfer destination, and transfer data count are read from the
descriptor.
4. A DMA transfer between I/O and memory starts.
5. For no transfer end: The interrupt request of a resource is cleared.
For transfer end: After the DMA transfer ends, the DMA status register is set to the transfer
end flag, thereby causing output of an interrupt request to the interrupt controller.
by IOA
(3)
(3)
by BAP
(4)
IOA : I/O address buffer
BAP : Buffer address pointer
DER : DMA enable register (also selects ENx)
DCT : Data counter
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Figure 3.6-1 µ µ µ µ DMA operations
Memory space
I/O register
DER
DMA descriptor
(2)
Buffer by DCT
Data transfer using DMA is
Peripheral function
I/O register
(I/O)
(1)
DMA controller
Interrupt
CPU
controller