Fujitsu F2MC-16LX Hardware Manual page 502

CHAPTER 26 2M BIT FLASH MEMORY
I Operation for writing to flash memory
Figure 26.6-1 "Example of the Flash Memory Write Procedure" shows an example of the
procedure for writing to flash memory. Using the hardware sequence flag (see Section 25.5,
"Verifying the Execution State of the Automatic Algorithm"), the operational state of the
automatic algorithm operating on the flash memory can be determined. In this example, the data
polling flag (DQ7) is used to indicate the end of writing.
During the flag check, data is read from the last address data was written to.
The data polling flag (DQ7) changes at the same time as the timing limit excess flag (DQ5).
Even if the timing limit excess flag (DQ5) is "1", the data polling flag bit (DQ7) must be checked
again.
Since the toggle bit flag (DQ6) also stops the toggle operation when the timing limit excess flag
bit (DQ5) is set to "1", the toggle bit flag (DQ6) must be checked again in this case.
Figure 26.6-1 Example of the Flash Memory Write Procedure
Write error
486
Start of write operation
FMCS:WE(bit5)
Enable flash memory write
Write command sequence
(1) FxAAAA XXAA
(2) Fx5554 XX55
(3) FxAAAA XXA0
(4) Write address write data
Internal address read
Data polling(DQ7)
Data
0
Timing limit(DQ5)
1
Internal address read
Data
Data polling(DQ7)
Data
Last address
FMCS:WE(bit5)
Flash memory write
prohibited
Write completed
Next address
Data
Check by hardware
sequence flag