Fujitsu F2MC-16LX Hardware Manual page 416

CHAPTER 21 UART
[Bit 12] CL: Character Length
This bit specifies the data length of one frame to be sent or received.
0
1
Note:
Only the normal mode (Mode 0) in asynchronous (start-stop) communications can handle 7-
bit data. Use 8-bit data only in multiprocessor mode (Mode 1) or CLK synchronous
communication (Mode 2).
[Bit 11] A/D: Address/Data
This bit specifies the data format for frames to be sent and received in multiprocessor mode
(Mode 1) during asynchronous (start-stop) communication.
0
1
[Bit 10] REC: Receiver Error Clear
This bit clears the error flags (PE, ORE, FRE) of the SSR Register.
Writing "1" has no effect. Read operations always return "1".
[Bit 9] REX: Receiver Enable
This bit controls the reception state of the UART.
0
1
If reception operation becomes disabled while reception is in progress (while data is input to
the reception shift register), reception operation will only be disabled after reception of the
frame is completed and the reception data is stored in the reception data buffer register
(SIDR).
[Bit 8] TEX: Transmitter Enable
This bit controls the UART transmission states.
0
1
If transmission operation becomes disabled while transmission is in progress (while data is
output from the transmission register), transmission operation will only be disabled after the
transmission data buffer register SODR no longer contains transmission data. Transmission
is resumed by synchronization with an internal serial clock after writing a value to the
transmission data buffer register (SODR). Disabling of transmission (TEX = 0) is invalid
when the TDRE Flag is "0".
400
7-bit data
8-bit data
Data frame
Address frame
Disables reception operation
Enables reception operation
Disables transmission operation
Enables transmission operation