Operational States Of Serial I/O Units - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 20 EXPANDED I/O SERIAL INTERFACE

20.3.2 Operational States of Serial I/O Units

Four serial I/O states are used, namely, STOP, Halt, SDR R/W Wait, and Transfer.
I Operational states of serial I/O units
❍ STOP State
The shift counter is initialized at reset or by writing "1" to the STOP bit of SMCS, resulting in SIR
= 0.
For returning from the STOP state, set STOP = 0 and STRT= 1 (these bits can be set
simultaneously). Because the STOP bit has a higher priority than the STRT bit, data transfer will
not be executed even when STRT = 1 is set while STOP = 1.
❍ Halt State
When the MODE Bit is set to "0", the BUSY and SIR bit of SMCS will become BUSY = 0 and
SIR = 1 after data transfer ends. The counter will then be initialized and set to the Halt state. For
returning from the Halt state, set STRT = 1 to resume data transfer operation.
❍ Serial Data Register R/W Wait State
When the MODE Bit of SMCS is "1" and serial transfer ends, this will result in BUSY = 0 and
SIR = 1 and the serial data register R/W Wait state will be entered. If the interrupt enable
register is set to "enable", the applicable block will issue an interrupt signal.
When returning from the R/W Wait state, data transfer operation will be resumed as soon as a
read or write operation is performed for the serial data register.
❍ Transfer State
In this state, serial transfer is performed if BUSY = 1. Depending on the setting of the MODE bit,
the Halt or R/W Wait state will be entered.
Figure 20.3-1 "State transitions during operation of expanded I/O serial interface" shows the
state transitions during operation. Figure 20.3-2 "Concept of read and write of serial data
registers" illustrates the concept of reading and writing the serial data register.
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