Block Diagram Of Address Match Detection Function - Fujitsu F2MC-16LX Hardware Manual

24.2 Block Diagram of Address Match Detection Function

The address match detection module consists of the following blocks:
• Address latch
• Address detection control register (PACSR)
• Detect address setting registers (RADR)
I Block Diagram of Address Match Detection Function
Figure 24.2-1 "Block Diagram of the Address Match Detection Function" shows the block diagram
of the address match detection function.
Figure 24.2-1 Block Diagram of the Address Match Detection Function
Detect address setting register 0
Detect address setting register 1
PACSR
Reserved
Address detection control register (PACSR)
Reserved: Always set to "0"
❍ Address latch
The address latch stores the value of the address output to the internal data bus.
❍ Address detection control register (PACSR)
The address detection control register enables or disables output of an interrupt at an address
match.
❍ Detect address setting registers (PADR0, PADR1)
The detect address setting registers set the address that is compared with the value of the
address latch.
Notes: The addresses of the detect address setting register are 1FF0
the RAM area. Therefore, the access to the RAM area should not be performed during the use
of this function.
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION
Address latch
PADR0 (24bit)
PADR1 (24bit)
Reserved Reserved Reserved AD1E Reserved AD0E
INT9 instruction
( INT9 interrupt
generation)
Reserved
to 1FF5 and are included in
H H
451