Fujitsu F2MC-16LX Hardware Manual page 344

CHAPTER 16 16-BIT RELOAD TIMER
❍ Operation in one-shot mode
If the counter value causes an underflow (0000
case, the underflow request flag bit (UF) is set to "1". If the interrupt request output enable bit
(INTE) is also set to "1", an interrupt request is generated. The TOT pin outputs a square wave
that indicates counting in progress. Figure 16.3-11 "Counter operation in one-shot mode (event
count mode)" shows the counter operation in one-shot mode.
Figure 16.3-11 Counter operation in one-shot mode (event count mode)
TIN pin
Counter
Data load signal
UF bit
CNTE bit
TRG bit
TOT pin
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width of clock input to the TIN pin shall be 4/φ or more.
328
Reload
-1 0000 FFFF
H
data
{1
T
Waiting for start trigger input
--> FFFF ), the counter stops at FFFF
H H
Reload
-1 0000
H
data
H
FFFF
H H
. In this