Individual Registers Of Dma Descriptor - Fujitsu F2MC-16LX Hardware Manual

3.6.2

Individual Registers of DMA Descriptor

Each DMA descriptor consists of the following registers:
• Data counter (DCT)
• I/O register address pointer (IOA)
• DMA control register (DMACS)
• Buffer address pointer (BAP)
The registers must be initialized because their initial values become undefined when
they are reset.
I Data counter (DCT)
The data counter (DCT) is a register with a length of 16 bits and corresponds to the transfer
data count. After each item of data is transferred, the counter decrements by one. If this
counter reaches zero, DMA ends. Figure 3.6-3 "Configuration of data counter (DCT)" shows the
configuration of the data counter (DCT).
If the data counter (DCT) is set to "0", the maximum data transfer count (i.e., 65536) is defined.
Bit 15 14 13
DCT B15 B14 B13 B12 B11
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/write allowed
x : Undefined
I I/O register address pointer (IOA)
The I/O register address pointer (IOA) is a register with a length of 16 bits, and it indicates the
lower address (A15 to A0) of the I/O register providing a buffer for data transfers. All of the
upper addresses (A23 to A16) are set to "0". Any I/O in a range of "000000
be specified with the address.
Figure 3.6-4 "Configuration of I/O register address pointer (IOA)" shows the configuration of the
I/O register address pointer (IOA).
Figure 3.6-4 Configuration of I/O register address pointer (IOA)
Bit
15 14 13
IOA A15 A14 A13 A12 A11
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/write allowed
x : Undefined
Figure 3.6-3 Configuration of data counter (DCT)
DCTH
12 11 10 09 08
B10 B09 B08 B07
IOAH
12 11 10 09 08
A10 A09 A08 A07
DCTL
05 04 03
07 06
B06 B05 B04 B03
IOAL
05 04 03
07 06
A06 A05 A04 A03
CHAPTER 3 INTERRUPT
02 01
00
Initial value
B02 B01 B00
XXXXXXXXXXXXXXXX
" to "00FFFF
H
02 01 00
Initial value
A02 A01 A00
XXXXXXXXXXXXXXXX
B
" can
H
B
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