Fujitsu F2MC-16LX Hardware Manual page 92

CHAPTER 3 INTERRUPT
I DMA control status register (DMACS)
The DMA control status register (DMACS) has a length of 8 bits that indicate the update or fixed
state, transfer data format (byte/word), and transfer directions for the buffer address pointer
(BAP) and I/O register address pointer (IOA). Figure 3.6-5 "Configuration of DMA control status
register (DMACS)" shows the configuration of the DMA control status register (DMACS).
Figure 3.6-5 Configuration of DMA control status register (DMACS)
05
Bit 07 06
RESV RESV RESV
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/write allowed
x : Undefined
*1 : The buffer address pointer changes at the lower 16 bits, and it can only be incremented.
*2 : I/O register address pointer can only be incremented.
76
04 03 02 01
IF BW BF DIR
SE
0
Operation is not ended by a request from a peripheral function.
1 Operation is ended by a request from a peripheral function.
DIR
0
I/O register address pointer -> buffer address pointer
Buffer address pointer → I/O register address pointer
1
BF
0
The buffer address pointer is updated after a data transfer.*1
1
The buffer address pointer is not updated after a data transfer.
BW
0
Byte
1
Word
IF
0
The I/O register pointer is updated after a data transfer.
1
The I/O register pointer is not updated after a data transfer.
RESV
Always set these bits to 0.
00
Initial value
XXXXXXXX
SE
B
DMA end control bit
Data transfer direction specify bit
BAP update/fixed selection bit
Transfer data length setting bit
IOA update/fixed selection bit
Reserve bit