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15.3.2 PPG1/3/5 Operation Mode Control Register
(PPGC1/PPGC3/PPGC5)
This section describes the configuration and functions of the PPG1/PPG3/PPG5
operation mode control register (PPGC1/PPGC3/PPGC5).
■
PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5)
The PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) is used to
select the channel 1/3/5 operation mode, control pin output, and select the count clock. It is also
used for trigger control.
The bit configuration of the PPG1/PPG3/PPG5 operation mode control register (PPGC1/
PPGC3/PPGC5) is shown below.
15
ch.1 00003B
H
ch.3 00003D
PEN1
H
ch.5 00003F
H
(R/W)
(0)
The functions of the bits in the PPG1/PPG3/PPG5 operation mode control register (PPGC1/
PPGC3/PPGC5) are described below.
[bit15] PEN1: ppg Enable (operation enable)
This bit is used to select the PPG operation mode.
PEN1
0
1
•
When this bit is set to "1", PPG count starts.
•
This bit is initialized to "0" at reset.
•
Reading and writing are allowed.
[bit13] PE10: ppg output Enable 10 (PPG1/PPG3/PPG5 output pin enable)
This bit is used to allow or prohibit pulse output to the pulse output external pin PPG1/PPG3/
PPG5.
PE10
0
1
•
This bit is initialized to "0" at reset.
•
Reading and writing are allowed.
14
13
12
11
-
PE10 PIE1 PUF1 MD1 MD0
(-)
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(0)
(0)
(0)
Operation stop ("L" level output is retained)
PPG operation enabled
General-purpose port pin (pulse output prohibited)
PPG1/PPG3/PPG5 pulse output (pulse output allowed)
CHAPTER 15 8/16-BIT PPG TIMER
10
9
8
PPGC1/3/5
Operation mode control register
Reserved
(-)
Read/write
(0)
(0)
(1)
Initial value
Operation state
Operation state
325
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