Fujitsu F2MC-16LX Hardware Manual page 368

CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT
I DTP operation
To start µDMA in a user program, the following initialization operations are performed: The I/O
address pointer in the µDMA descriptor is set to the register address allocated in 000000
0000FF
H
The operational sequence for DTP is almost the same as that for external interrupts. In
particular, the operational sequence until the CPU starts the microprogram for handling
hardware interrupts is exactly the same. At the start of µDMA, the corresponding read or write
signal is transferred to the external peripheral device whose address was specified, and data
transfer is performed. Ensure that the external peripheral device withdraws the interrupt request
within three machine cycles after data transfer. At the end of data transfer, the descriptor is
updated, and a signal to clear the interrupt source is generated by the interrupt controller. After
receiving the signal, the DTP unit clears the flip-flop that retains the interrupt source and waits
for the next request.
Figure 18.3-2 "Timing for withdrawing an external interrupt request at the end of DTP operation"
shows the timing for withdrawing the external interrupt signal at the end of DTP operation.
Figure 18.3-3 "Example of interface with an external peripheral device" shows an example for
an interface with the external peripheral device.
Figure 18.3-2 Timing for withdrawing an external interrupt request at the end of DTP operation
Interrupt source
Internal operation
Address bus pin
Data bus pin
Read signal
Write signal
Figure 18.3-3 Example of interface with an external peripheral device
Data bus or
address bus
IRQ
Withdrawn within 3 machine
cycles after the end of transfer
352
, and the buffer address pointer is set to the start address of the memory buffer.
↑ Rising edge request or "H"-level request
Descriptor
selection/read
DTP
MB90470
* µDMA for transferring
from I/O register to memory
Read address Write address
Read data
(1)
Withdrawn within 3 machine cycles
Internal bus
(1)
INT
CORE
Write data
(2)
(2)
MEMORY
-
H