Serial Status Register (Ssr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART

21.2.4 Serial Status Register (SSR)

This section describes the configuration and functions of the serial status register
(SSR).
I Serial status register (SSR)
The bit configuration of the serial status register (SSR) is illustrated below.
15
000023 PE
H
(R)
(0)
The SSR provides a flag that represent the UART status.
The functions of the serial status register (SSR) bits are described below.
[Bit 15] PE: Parity Error
This bit acts as an interrupt request flag that is set when a parity error occurs during
receiving. Set the REC bit (bit 10) of the SSR register to "0" to clear a flag that has been set.
The data in the SIDR becomes invalid when this bit is set.
0
1
[Bit 14] ORE: Over Run Error
This bit is an interrupt request flag that is set in case an overrun error occurs during
reception. Set the REC bit (bit 10) of the SSR register to "0" to clear a flag that has been set.
The data in the SIDR becomes invalid when this bit is set.
0
1
[Bit 13] FRE: FRaming Error
This bit is an interrupt request flag that is set in case a framing error occurs during reception.
Set the REC bit (bit 10) of the SSR register to "0" to clear a flag that has been set. The data
in the SIDR becomes invalid when this bit is set.
0
1
[Bit 12] RDRF: Receiver Data Register Full
This bit is an interrupt request flag that indicates that the SIDR register has stored reception
data. This flag is set when reception data is loaded into the SIDR register and is cleared
automatically when the SIDR register is reads.
402
14 13 12 11
ORE FRE RDRF TDRE BDS
(R) (R) (R) (R) (R/W) (R/W) (R/W) Reading/writing
(0) (0) (0) (1)
No parity error
Parity error detected
No overrun error
Overrun error detected
No framing error
Framing error detected
10 9 8
RIE TIE Serial status register (SSR)
(0) (0) (0) Initial value