Fujitsu F2MC-16LX Hardware Manual page 62

CHAPTER 3 INTERRUPT
Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (Continued)
Interrupt factor
Output compare (channel 4)
match
Output compare (channel 5)
match
UART transmit completed
16-bit free-running timer/16 reload
timer overflow
UART receive completed
SI01
SI02
2
I C interface
A/D
FLASH write/delete, timebase
timer, interval interrupt
(watch timer)
Delay interrupt generation module
: Interrupt request flag cleared by the interrupt clear signal. The stop request is available.
: Interrupt request flag cleared by the interrupt clear signal.
: Interrupt request flag not cleared by the interrupt clear signal.
If the same interrupt number has two interrupt factors, both of their interrupt request flags are cleared by the
2
EI OS/DMAC interrupt clear signal for a resource. If one of the two factors then uses the EI
function, the other interrupt function is not allowed to use it. Set the interrupt request permit bit of the relevant
resource to "0" so that software polling processing can handle it.
46
µ µ µ µ DMA
2
EI OS
channel
support
number
Number
11
12
7
13
14
15
Interrupt vector
Address Number
#32 FFFF7C
H
#33 FFFF78 ICR11
H
#34 FFFF74
H
#35 FFFF70 ICR12
H
#36 FFFF6C
H
#37 FFFF68 ICR13
H
#38 FFFF64
H
#39 FFFF60 ICR14
H
#40 FFFF5C
H
#41 FFFF58 ICR15
H
#42 FFFF54
H
Interrupt control
register
Address
0000BB
H
0000BC
H
0000BD
H
0000BE
H
0000BF
H
2
OS/µDMA