Overview Of Chip Selection Facility - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 23 CHIP SELECTION FACILITY

23.1 Overview of Chip Selection Facility

The chip selection facility is a module used to generate a chip selection signal for
simplified external connection of memory. It contains four chip selection output pins.
The chip selection facility enables a memory area within the hardware to be specified
via an output setting register, and if the device detects an access to that external
address, it outputs a selection signal via the corresponding pin.
I Features of the chip selection facility
The chip selection facility contains two 8-bit registers for each output pin. One register (CARx) is
used to specify the upper 8 bits of the corresponding detection address, allowing addresses
within 64 KB to be specified. Another register (CMRx) is used to mask the corresponding bits of
the address so that values above 64 KB can be specified for the area to be detected.
In external bus hold mode, CS output is set to high impedance mode.
I Block diagram of the chip selection facility
Figure 23.1-1 "Block diagram of the chip selection facility" shows a block diagram of the chip
selection facility.
CMRx
CARx
A23-16
440
Figure 23.1-1 Block diagram of the chip selection facility
Chip selection pin output