Fujitsu F2MC-16LX Hardware Manual page 561

Table B.8-12 18 Shift instructions (byte, word, long word)
Mnemonic #
RORC A 2
ROLC A 2
RORC ear 2
RORC eam 2+
ROLC ear 2
ROLC eam 2+
ASR A,R0 2
LSR A,R0 2
LSL A,R0 2
ASRW A 1
LSRW A/SHRW A 1
LSLW A/SHLW A 1
ASRW A,R0 2
LSRW A,R0 2
LSLW A,R0 2
ASRL A,R0 2
LSRL A,R0 2
LSLL A,R0 2
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
RG B
2 0 0 byte (A) <-- With right rotation carry
2 0 0 byte (A) <-- With left rotation carry
3 2 0 byte (ear) <-- With right rotation carry
5+(a) 0 2 x (b) byte (eam) <-- With right rotation carry
3 2 0 byte (ear) <-- With left rotation carry
5+(a) 0 2 x (b) byte (eam) <-- With left rotation carry
*1 1 0 byte (A) <-- Arithmetic right shift (A, 1 bit)
*1 1 0 byte (A) <-- Logical right barrel shift (A, R0)
*1 1 0 byte (A) <-- Logical left barrel shift (A, R0)
2 0 0 word (A) <-- Arithmetic right shift (A, 1 bit)
2 0 0 word (A) <-- Logical right shift (A, 1 bit)
2 0 0 word (A) <-- Logical left shift (A, 1 bit)
*1 1 0 word (A) <-- Arithmetic right barrel shift (A, R0)
*1 1 0 word (A) <-- Logical right barrel shift (A, R0)
*1 1 0 word (A) <-- Logical left barrel shift (A, R0)
*2 1 0 long (A) <-- Arithmetic right barrel shift (A, R0)
*2 1 0 long (A) <-- Logical right barrel shift (A, R0)
*2 1 0 long (A) <-- Logical left barrel shift (A, R0)
Operation L
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APPENDIX B Instructions
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